The present invention relates generally to a logic module or macrocell for use in programmable logic devices. More particularly, the present invention provides a highly flexible and fast macrocell with enhanced logic capability.
The fundamental building block of a PLD is a macrocell. Each macrocell is capable of performing limited logic functions on a number of input variables. Broadly, a macrocell includes a programmable AND array whose output terms feed a fixed OR array to implement the "sum of products" logic. When combined together in large numbers inside a PLD, macrocells facilitate implementation of complex combinatorial as well as sequential logic.
One approach to implementing a macrocell utilizes a programmable memory structure that includes architecture bits for storing information corresponding to a desired logic configuration. The memory structure is then connected to a look-up table that implements any logical function of its several input variables. To be able to perform sequential logic, the output of the look-up table also feeds an input of a configurable register. A macrocell thus constructed offers advantages in speed, density, programming flexibility, and manufacturing ease. However, there is always room for improvement in terms of logic capability and speed performance.
A macrocell can be designed with as many logic inputs as required by the logic operations. Complex logic operations tend to require a high number of input variables. Thus, increasing the fan-in of a macrocell enhances its logic capability. However, a linear increase in the fan-in of a look-up table results in a geometric increase in the number of programmable architecture bits required to implement the look-up table. For example, a 4-input programmable look-up table requires 16 (2.sup.4) programmable architecture bits to implement any 4-variable logic function. An 8-input programmable look-up table requires 256 (2.sup.8) programmable architecture bits to implement any 8-variable logic function.
From the manufacturing perspective, a greater number of programmable architecture bits per macrocell means higher circuit density and lower yield. In practical terms, this circuit density constraint places an upper limit on the number of programmable architecture bits and consequently the look-up table fan-in. Thus, while designers have always searched for ways to increase the logic capability of PLDs, one challenge has been to balance the macrocell fan-in against this circuit density constraint.
A successful method of increasing the logic capability of PLDs while keeping circuit density within acceptable levels is disclosed in a commonly-assigned U.S. patent application, Ser. No. 08/049,064 (Attorney Docket No. 15114-369), which is hereby incorporated by reference in its entirety, and the references cited therein. There, it was recognized that while cascading multiple macrocells together increases the number of input variables, it results in inefficient use of circuitry in a PLD. Therefore, logic capability of each macrocell was increased by including more than one look-up table in each macrocell. The outputs of the plurality of look-up tables were logically combined inside each macrocell, enabling it to perform more complex logic operations involving larger number of variables.
While this technique improves the capability of a macrocell to perform more complex combinatorial logic, registered (or sequential) logic capacity and speed performance of the PLD remain unaffected. Register count of a PLD is important for high density register mode applications, while speed is especially critical in applications using sequential logic where setup time can be a limiting factor. Setup time refers to the time it takes an input data to propagate from the input pin on the chip to the input of the first clocked register inside a macrocell.
Simply increasing the number of macrocells in a PLD to obtain a larger register count for high density register mode applications may result in unacceptably large die sizes. Silicon area considerations place an upper limit on the number of macrocells and thus the number of registers available for existing PLDs.
For a typical macrocell, in order for the input signal to reach the input of a clocked register, it must first propagate through the look-up table or product term logic. Furthermore, typical PLD architectures require the input signal to first connect to some type of global interconnect network, go through a selection logic and cross a local array of macrocells before it arrives at an input of a particular macrocell. Therefore, the total signal propagation delay includes the delay associated with the heavily loaded global interconnect lines, gate delays through the selection logic (e.g. multiplexers), delay through the interconnect line crossing the local macrocell array, and delay associated with the macrocell logic. This propagation delay can be as high as, for example, 10 nanoseconds.
From the foregoing, it can be appreciated that there is a need for a macrocell with improved logic capability that provides for larger register count and a fast setup time in programmable logic devices with comparable die sizes.